Yuanlong Li (李元龙)

PhD Student

Yuanlong Li

I am a final-year Ph.D. student in the School of Computer and Communication Sciences (IC) at École Polytechnique Fédérale de Lausanne (EPFL). I am advised by Prof. Babak Falsafi and am affiliated with Parallel Systems Architecture Lab (PARSA).

I am broadly interested in systems and cross-stack research problems in modern, large-scale datacenters. I mainly work on the hardware side, but I also keep an eye on software and AI. My current research focuses on designing high-performance and secure Function-as-a-Service (FaaS) serverless systems in datacenters. I am one of the main PhD students in the Intel-funded project Midgard, aiming at redesigning virtual memory for higher performance and efficiency of datacenter servers.

I am currently on the job market. Please contact me through email yuanlong.li@epfl.ch or WeChat. You can find my CV here.

News

  • Apr. 2026 Jord was selected as an IEEE MICRO TopPicks 2026 Honorable Mention!
  • May 2025 Flex 3.0 got accepted by AGPC ’25!
  • Mar. 2025 Single-address-Space FaaS with Jord got accepted by ISCA ’25!
  • Feb. 2025 IOMMU got accepted by YArch ’25!
  • Dec. 2024 Passed PhD proposal exam.
  • Mar. 2023 SecureCells got accepted by Oakland ’23!
  • Mar. 2023 Imprecise Store Exceptions got accepted by ISCA ’23!
  • Sep. 2021 Passed PhD candidacy exam.
  • Oct. 2021 Started PhD at EPFL.

Conference Papers

ISCA ’25 Single-Address-Space FaaS with JordISCA ’23 Imprecise Store Exceptions
  • On the implications of deeper memory hierarchies for precise exceptions
  • Yuanlong Li*, Siddharth Gupta*, Qingxuan Kang, Abhishek Bhattacharjee, Babak Falsafi, Yunho Oh, and Mathias Payer. 2023. Imprecise Store Exceptions. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ’23), June 17–21, 2023, Orlando, FL, USA. (* Equal contribution)
Oakland ’23 SecureCells: A Secure Compartmentalized Architecture
  • Novel virtual memory architecture for secure, efficient and flexible compartmentalization
  • Atri Bhattacharyya, Florian Hofhammer, Yuanlong Li, Siddharth Gupta, Andres Sanchez, Babak Falsafi, and Mathias Payer. 2023. SecureCells: A Secure Compartmentalized Architecture. In Proceedings of the 44th IEEE Symposium on Security and Privary (IEEE S&P 2023), May 22–24, San Francisco, CA, USA.

Workshop Papers / Preprints

arXiv SystolicAttention: Fusing FlashAttention within a Single Systolic Array
  • Enhancing systolic array architecture for reduction operations in FlashAttention
  • Jiawei Lin, Guokai Chen, Yuanlong Li, and Thomas Bourgeat. 2025. SystolicAttention: Fusing FlashAttention within a single Systolic Array. July 2025. arXiv:2507.11331 [cs].
AGPC ’25 QFlex 3.0: Fast and Accurate ARM Server Simulation
  • The next version of QFlex simulator with sampling methodology
  • Shanqing Lin, Ali Ansari, Ayan Chakraborty, Bugra Eryilmaz, Yuanlong Li, Mohammad Alian, and Babak Falsafi. 2025. QFlex 3.0: Fast and Accurate ARM Server Simulation. In the 1st ARM-based General-Purpose Computing Workshop (APGC ’25), co-located with ISCA ’25, June 21, 2025, Tokyo, Japan.
YArch ’25 Rethinking IOMMU for Future IO Devices

Talks

  • Institute of Computing Technology, Chinese Academy of Sciences 2025
    • Single-Address-Space FaaS with Jord
  • Institute of Computing Technology, Chinese Academy of Sciences 2023
    • Imprecise Store Exceptions

    Services

    • MICRO'26 Program Committee 2026
    • HPCA'24 Artifect Evaluation Committee 2024

      Awards

      • IEEE MICRO TopPicks Honorable Mention 2026
      • EPFL EDIC Fellowship 2020
      • Graduate First-class Academic Scholarship 2015
      • National Encouragement Scholarship 2013
      • National Encouragement Scholarship 2011

      Education

      Work Experiences

      • SiFive China, Inc. Feb. 2020 – Sep. 2020
      • ARM China, Inc. May 2019 – Jan. 2020
        • Engineer
        • Designer of the cryptographic co-processor for ARMv8-M CPUs
      • Unisoc, Inc. Jul. 2017 – May 2019
        • Advanced Senior ASIC Design Engineer
        • Designer of L1/L2 TLBs of Unisoc’s second CPU
        • Full-system verification, emulation, FPGA prototyping, and post-silicon validation of Unisoc’s CPUs (1.6 GHz@TSMC 28nm, 2-issue InO SMT, ARMv8-A)

      Projects