I am a fifth-year Ph.D. student in the School of Computer and Communication Sciences (IC) at École Polytechnique Fédérale de Lausanne (EPFL). I am advised by Prof. Babak Falsafi and am affiliated with Parallel Systems Architecture Lab (PARSA).

I am broadly interested in systems and cross-stack research problems in modern, large-scale datacenters. I mainly work on the hardware side, but I also keep an eye on software and AI. My current research focuses on designing high-performance and secure Function-as-a-Service (FaaS) serverless systems in datacenters. I am one of the main PhD students in the Intel-funded project Midgard, aiming at redesigning virtual memory for higher performance and efficiency of datacenter servers.

I am currently open to the job market. Please contact me through email yuanlong.li@epfl.ch or WeChat (QR code below). You can find my CV here.

Conference Proceedings

ISCA ’25 Single-Address-Space FaaS with Jord

• Yuanlong Li, Atri Bhattacharyya, Madhur Kumar, Abhishek Bhattacharjee, Yoav Etsion, Babak Falsafi, Sanidhya Kashyap, and Mathias Payer. 2025. Single-Address-Space FaaS with Jord. In Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA ’25), June 21-25, 2025, Tokyo, Japan.

ISCA ’23 Imprecise Store Exceptions

• On the implications of deeper memory hierarchies for precise exceptions
• Yuanlong Li*, Siddharth Gupta*, Qingxuan Kang, Abhishek Bhattacharjee, Babak Falsafi, Yunho Oh, and Mathias Payer. 2023. Imprecise Store Exceptions. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ’23), June 17–21, 2023, Orlando, FL, USA. (* Equal contribution)

Oakland ’23 SecureCells: A Secure Compartmentalized Architecture

• Novel virtual memory architecture for secure, efficient and flexible compartmentalization
• Atri Bhattacharyya, Florian Hofhammer, Yuanlong Li, Siddharth Gupta, Andres Sanchez, Babak Falsafi, and Mathias Payer. 2023. SecureCells: A Secure Compartmentalized Architecture. In Proceedings of the 44th IEEE Symposium on Security and Privary (IEEE S&P 2023), May 22–24, San Francisco, CA, USA.

Talks

• Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China2023
  • Imprecise Store Exceptions

Work Experiences

• SiFive China, Inc.Feb. 2020 – Sep. 2020
  • Senior Engineer
  • Designer of Load/Store Unit (LSU) and L2 cache controller (L2C) of SiFive China’s first server CPU core (2 GHz@TSMC 12nm, 5-issue OoO, RV64GCBH)
• ARM China, Inc.May 2019 – Jan. 2020
  • Engineer
  • Designer of the cryptographic co-processor for ARMv8-M CPUs
• Unisoc, Inc.Jul. 2017 – May 2019
  • Advanced Senior ASIC Design Engineer
  • Designer of L1/L2 TLBs of Unisoc’s second CPU
  • Full-system verification, emulation, FPGA prototyping, and post-silicon validation of Unisoc’s CPUs (1.6 GHz@TSMC 28nm, 2-issue InO SMT, ARMv8-A)

Projects

I mostly work full-stack, from RTL, FPGA, CPU microarchitecture, to OS and applications.

• QFlex
  • A family of full system simulators based on QEMU and Flexus
• SecureCells on RocketChip
  • RTL implementation of SecureCells on RocketChip
• Midgard
  • RTL implementation of Midgard/Jord
• Midgard on OpenXiangShan
  • Integration of Midgard/Jord and OpenXiangShan
• Midgard Linux
  • Linux port of Midgard/Jord
• XiangShan over FireSim
  • Running OpenXiangShan over FireSim